1. Field of the Invention
The present invention relates to a designing method of a semiconductor integrated circuit. Particularly, the present invention relates to a designing method of a semiconductor integrated circuit using a library storing a mask pattern of a macro circuit.
2. Description of the Related Art
When a layout of a semiconductor integrated circuit is designed, a macro circuit is used which is a circuit block having a certain function. The usage of the macro circuit facilitates design of the layout.
A layout method for a semiconductor integrated circuit using a macro circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 1-293534) and corresponding Japanese Patent No. 2575180. In the known layout method, mega-cells 101, 102 and 103 constituted by combinations of a plurality of standard cells are arranged as shown in FIG. 1. A macro circuit 101 has terminals Pa1 to Pa3, terminals Pb1 to Pb3 and terminals Pc1 to Pc3. The terminals Pa1 to Pa3, the terminals Pb1 to Pb3 and the terminals Pc1 to Pc3 are located in a plurality of sides on a rectangular area defining the macro circuit 101. Wirings connected to the macro circuit 101 are connected to the terminals Pa1 to Pa3, the terminals Pb1 to Pb3 and the terminals Pc1 to Pc3. The known layout method protects the mounted wiring from bypassing the macro circuit 101.
However, an output buffer for outputting a signal from the macro circuit is not noted in the above-mentioned Japanese Laid Open Patent Application (JP-A-Heisei 1-293534) and corresponding Japanese Patent No. 2575180.
Another layout method for a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 4-78153). In this known layout method, a logical cell array 202, memories 204, 205 and input/output buffer cell 206s are mounted in a semiconductor integrated circuit 201, as shown in FIG. 2. A large number of logical cells 203, which are small-scale macro cells, are mounted in the logical cell array 202. The memories 204, 205 are large-scale macro cells. The input/output buffer cells 206 are small-scale macro cells. In this known semiconductor integrated circuit, the wiring between the small-scale macro cells is laid so as to bypass the memories 204, 205.
At first, terminal extension areas 211, 212 and 213 are defined around the memories 204 and 205, as shown in FIG. 3. Terminals of the logical cells 203 and the input/output buffer cells 206, are extensively laid in the terminal extension areas 211, 212 and 213. Extensive positions 211a, 212a and 213a of the terminal are defined as tip ends of the terminal extension areas 211, 212 and 213.
Moreover, extensive routes 211b, 212b and 213b are defined from the terminal of the input/output buffer cell 206 to the respective extensive positions 211a, 212a and 213a, as shown in FIG. 4.
Moreover, as shown in FIG. 2, a terminal B of the input/output buffer cell 206 is extended up to the respective extensive positions 211a, 212a and 213a along the extensive routes 211b, 212b and 213b. The extended terminal B is referred to as an extensive terminal B1 hereinafter. The extensive terminal B1 is connected to a terminal A of the logical cell 203.
This known layout method can shorten a time required to find out a wiring route of a wiring for connecting the logical cell 203 and the input/output buffer cell 206.
Also, still another layout method for a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 11-260923). In this known layout method for the semiconductor integrated circuit, a spare cell is mounted in addition to usage cells. When the design of the circuit is changed, the spare cell is used to easily change the circuit. This known layout method relates to the layout method for the spare cell.
A spare cell having a structure shown in FIG. 5 is firstly placed in designing a semiconductor integrated circuit. The spare cell is provided with a P-type MOS transistor 301 and an N-type MOS transistor 302. A source 301a of the P-type MOS transistor 301 and a source 302a of the N-type MOS transistor 302 are respectively connected through wirings 307, 306 to a ground line 316. Both the sources 301a, 302a are electrically separated from a power supply line 315.
When a circuit included in the semiconductor integrated circuit is changed, the spare cell is used. When the spare cell is used, its structure is changed as shown in FIG. 6. The source 301a of the P-type MOS transistor 301 is separated from the ground line 316 and connected through a wiring 310 to the power supply line 315. Thus, the spare cell serves as an inverter. The usage of the spare changes the circuit included in the semiconductor integrated circuit.
When the spare cell placed in this known layout method is at a non-usage state, there is no route through which a current flows from the power supply cell 315 to the ground line 316. Thus, it is possible to reduce a consumptive current in the semiconductor integrated circuit designed on the basis of this known layout method.
Also, a semiconductor integrated circuit in which a consumptive current is reduced is disclosed in Japanese Laid Open Patent Application (JP-A-Showa, 62-23131). In this known semiconductor integrated circuit, a usage unit cell 404 and a non-usage unit cell 404A are mounted as shown in FIG. 7. In the usage unit cell 404, MISFETs Qpxe2x80x2, Qnxe2x80x2 are connected through a wiring 416xe2x80x2 to each other. The MISFETs Qpxe2x80x2, Qnxe2x80x2 constitute an inverter. An output signal of the inverter is outputted from the wiring 416xe2x80x2. On the other hand, the non-usage unit cell 404A contains MISFETs Qp, Qn. A wiring 416 is cut away, and drain areas 410, 411 of the MISFETs Qp, Qn are electrically separated from each other. Thus, it is possible to reduce a consumptive current in the semiconductor integrated circuit.
However, an arrangement of a macro circuit is not noted in Japanese Laid Open Patent Application (JP-A-Heisei, 11-260923 and JP-A-Showa 62-23131).
An object of the present invention is to provide a wiring method for a semiconductor integrated circuit, in which a wiring included in the semiconductor integrated circuit can be designed so as not to bypass a macro circuit, an apparatus for wiring a semiconductor integrated circuit, and a macro library.
Another object of the present invention is to provide a wiring method for a semiconductor integrated circuit, which can reduce a consumptive power of a designed semiconductor integrated circuit, an apparatus for wiring a semiconductor integrated circuit, and a macro library.
Still another object of the present invention is to provide a wiring method for a semiconductor integrated circuit, in which a wiring included in the semiconductor integrated circuit can be designed so as not to bypass a macro circuit, and further a consumptive power of the designed semiconductor integrated circuit is reduced, an apparatus for wiring a semiconductor integrated circuit, and a macro library.
In order to achieve an aspect of the present invention, a designing method of a semiconductor integrated circuit is composed of providing a library storing a macro mask pattern for a macro circuit including buffer circuits, selecting one of the buffer circuits as a selected buffer circuit and arranging the macro mask pattern and a third wiring pattern to produce an integrated circuit mask. Each of buffer circuits is composed of first and second wirings apart from each other, and first and second semiconductor elements. The first semiconductor element selectively supplies the first wiring with a power supply potential in accordance with the output signal. The second semiconductor element selectively supplies the second wiring with a grounded potential in accordance with the output signal. The macro mask pattern includes buffer mask patterns, each of which corresponds to one of the buffer circuits. Each of the buffer mask patterns is composed of a first wiring pattern for the first wiring, and a second wiring pattern for the second wiring. In the integrated circuit mask pattern, the first and second wiring patterns of the selected buffer circuit are connected with each other by the third wiring pattern.
The first semiconductor element is desirably a P-channel MISFET including a first source connected to a power supply line having a power supply voltage, a first drain connected to said first wiring, and a first gate having a first gate voltage in response to said output signal.
The second semiconductor element is desirably an N-channel MISFET including a second source connected to a grounded line, a second drain connected to said first wiring and a second gate having a first gate voltage in response to said output signal.
The macro mask pattern may be accommodated in a rectangular area having four sides. In this case, one of said plurality of buffer mask patterns is located on one of said four sides, and another one of said plurality of buffer mask patterns is located on another one of said four sides.
The integrated circuit mask pattern may include a cell mask pattern for a cell included said semiconductor integrated circuit and said third wiring is connected to said cell. In this case, said selected buffer circuit is selected such that said third wiring is as short as possible.
In order to achieve another aspect of the present invention, a designing apparatus of a semiconductor integrated circuit is composed of a library and an arrangement wiring tool. The library stores a macro mask pattern for a macro circuit. The macro circuit includes an inner circuit outputting an output signal and a plurality of buffer circuits. Each of the plurality of buffer circuits is composed of first and second wirings apart from each other, a first semiconductor element selectively supplying said first wiring with a power supply potential in accordance with said output signal, and a second semiconductor element selectively supplying said second wiring with a grounded potential in accordance with said output signal. The macro mask pattern includes a plurality of buffer mask patterns, each of which corresponds to one of said plurality of buffer circuits. Each of said plurality of buffer mask patterns is composed of a first wiring pattern for said first wiring and a second wiring pattern for said second wiring. The arrangement wiring tool selects one of said plurality of buffer circuits as a selected buffer circuit. The arrangement wiring tool arranges said macro mask pattern and a third wiring pattern for a third wiring to produce an integrated circuit mask pattern based on said library such that said first and second wiring patterns of said selected buffer circuit are connected with each other by said third wiring pattern.
In order to achieve still another aspect of the present invention, a computer-readable recording medium records a library for designing an integrated circuit. The library is composed of a macro mask pattern for a macro circuit. The macro circuit includes an inner circuit outputting an output signal and buffer circuits. Each of the buffer circuits is composed of first and second wirings apart from each other, and first and second semiconductor elements. The first semiconductor element selectively supplies the first wiring with a power supply potential in accordance with the output signal. The second semiconductor element selectively supplies the second wiring with a grounded potential in accordance with the output signal. The macro mask pattern includes buffer mask patterns, each of which corresponds to one of the buffer circuits. Each of the buffer mask patterns is composed of a first wiring pattern for the first wiring, and a second wiring pattern for the second wiring.